TSMC eyes future technology with $1.4bn ASML investment
- 6 August 2012
- From the section Business
Taiwan Semiconductor Manufacturing Company, the world's biggest contract chipmaker, has agreed to invest 1.1bn euros ($1.4bn; £850m) in one of its key equipment suppliers in a bid to cut costs.
Under the deal, it will invest 276m euro in ASML to develop tools to make smaller, more cost-effective chips.
This comes just weeks after Intel signed a similar agreement with ASML.
Dutch firm ASML makes machines used to print circuit patterns onto chips.
Shang-yi Chiang, TSMC's co-chief operating officer, said that one of the biggest challenges facing the industry was "how to effectively control the escalating wafer manufacturing cost".
He said the co-investment programme with ASML to develop future technology will help keep the costs in check in the long run.
The Taiwanese chipmaker will also invest 838m euro to acquire a 5% stake in the firm.
Larger wafer size
TSMC said that it was hopeful that an increased investment in research will help ASML develop equipment that can handle a larger size of circular wafers from which chips are cut.
Chipmakers across the globe have been trying to increase the size of the wafers to 450mm, from the current size of 300mm.
The shift in the size of these wafers is expected to result in substantial cost savings for the chipmakers as more chips can be cut from them.
"The transition from one wafer size to the next has historically delivered a 30 to 40% reduction in die cost and we expect the shift from today's standard 300mm wafers to larger 450mm wafers to offer similar benefits," Brian Krzanich, Intel's chief operating officer said after the firm signed its agreement with ASML.
"The faster we do this, the sooner we can gain the benefit of productivity improvements, which creates tremendous value for customers and shareholders."
At the same time, TSMC and Intel have both said that their investment ASML will also help in faster development of extreme ultraviolet lithography, a new way of printing circuit patterns onto silicon wafers.
The technique is considered by many analysts as key to further reduction in the size of the chips.